Thin film transistors (TFTs) can be divided into polycrystalline silicon (P-Si) TFTs and amorphous silicon (a-Si) TFTs, and the difference between these kinds lies in the characteristics of an active layer. The P-Si crystalline structure within a grain is ordered and directional, so the carrier mobility therein is 200-300 times faster than that in amorphous silicon, in which the crystalline structure is arranged disordered. P-Si products mainly include two types of products: high-temperature Poly-Silicon (HTPS) and low-temperature Poly-Silicon (LTPS), and these two types can basically be divided depending on the crystallization temperature higher or lower than 600 degrees Celsius.
LTPS technology is the a new generation of manufacturing process of a TFT display, which mainly uses processes such as excimer laser annealing (ELA), metal induced crystallization (MIC) or solid phase crystallization (SPC) to convert an a-Si thin film into a P-Si thin film layer. A display using LTPS TFTs as driving elements has a faster response, a higher resolution, and thus has a better picture display quality. In the formation of the peripheral circuit of a display device, the LTPS technology can be used to reduce amount of the integrated circuits (IC), and thus simplify the periphery of the display device, so as to realize a narrow-frame technology.
As illustrated in FIG. 1, a conventional LTPS TFT array substrate comprises from bottom to top: a glass substrate 101, a buffer layer 102, a channel region 103, a gate insulating layer 105, a gate electrode 106, source-drain electrodes 104, an interlayer insulating layer 107, a passivation layer 108, a pixel electrode layer 109 and a pixel electrode insulating protective layer 110. The pixel electrode insulating protective layer 110 is applicable for LTPS AMOLED (Active Matrix Organic Light Emitting Diode), but if the product is an LTPS LCD (Liquid Crystal Display), then it may not comprise such layer. The traditional preparation process of an LIPS TFT array substrate is a 7-Mask process, which may comprise the following processes. Each mask is used in one patterning process.
A first mask (P-Si Mask): a pattern for both a TFT source-drain region and a channel region is formed.
Firstly, on the glass substrate 101, a SiNx/SiO2 buffer layer 102 is formed, then a layer of amorphous silicon (a-Si) thin film is deposited on the buffer layer 102, and through an LTPS crystallization method (such as ELA, MIC, SPC or the like), the amorphous silicon thin film is converted into a polycrystalline silicon thin film. Then, a photoresist layer is coated on the Poly-Silicon thin film; with the first Mask, the photoresist layer is exposed corresponding to an active layer pattern, and after exposure, it is developed to obtain a photoresist pattern; then, by using the photoresist pattern, the Poly-Silicon thin film is etched, and after removing the remaining photoresist, the channel region 103 is thus obtained.
A second mask (gate-metal-layer Mask): the gate electrode pattern 106 and the gate line pattern (not illustrated) are formed.
On the basis of the pattern formed with the first Mask, a gate insulating layer thin film 105 and a gate metal layer thin film are deposited, and the gate insulating layer thin film 105 may be of SiO2/SiNx; then, the gate metal layer thin film is coated thereon with photoresist, and with the second Mask, the photoresist layer is exposed; after developing, etching, photoresist-removing, the gate electrode pattern 106 and the gate line pattern are formed.
On the basis of the pattern formed with the second Mask, with the gate electrode pattern above the channel region pattern 103 as an ion-doping barrier layer, ion-doping is performed with respect to the source-drain region, as illustrated in FIG. 2-1. After ion-doping, an ion-doped region 111 is formed in the source-drain region. By ion-doping, the original regularly-crystallized Poly-Silicon crystal lattice is destroyed; in order to repair the Poly-Silicon crystal lattice, the Poly-Silicon layer should undergo an annealing treatment. The annealing treatment functions for restructuring Poly-Silicon crystal lattice and diffusing dopant-ions, as illustrated in FIG. 2-2. In the annealing process, dopant-ions will diffuse in the direction of the channel region 103 (illustrated by the arrows), as illustrated in FIG. 2-3.
A third Mask (gate insulating layer via-hole (GI Hole) Mask): contact holes for Poly-Silicon in the source-drain region and the source-drain electrodes are formed.
On the pattern after the complete of the second Mask, an interlayer insulating layer 107 is formed; then, the interlayer insulating layer 107 is coated thereon with photoresist, and with the third Mask, the photoresist layer is exposed corresponding to the source-drain electrode via-holes; after exposure, a development process and then an etching process are conducted, and at last the photoresist is removed.
The fourth mask (source-drain metal layer Mask): the source-drain electrode pattern 104 and the data line pattern (not illustrated) are formed.
On the basis of the pattern formed with the third mask, a source-drain metal layer thin film is deposited; then, the metal layer thin film is coated thereon with photoresist, and with the fourth mask, the photoresist layer undergoes exposure, development, etching, photoresist-removing; in this way, the formation of the source-drain electrode pattern 104 and the data line pattern is completed.
A fifth Mask (passivation layer via-hole (PVX Hole) Mask): bridge-holes for bridging the source-drain electrode pattern 104 are formed.
On the basis of the pattern formed with the fourth Mask, a passivation layer 108 is deposited; with the fifth mask, passivation layer via-holes are formed on the passivation layer 108.
A sixth Mask (pixel electrode Mask): the pixel electrode pattern 109 is formed.
On the basis of the pattern formed with the fifth Mask, a pixel electrode layer thin film is deposited; with the sixth Mask, it undergoes exposure, development, etching and photoresist-removing, thereby forming the pixel electrode pattern 109.
A seventh Mask (pixel electrode edge protection layer Mask): the pixel edge protective layer pattern is formed.
On the basis of the pattern formed with the sixth Mask, a protective layer thin film is deposited; with the seventh Mask, an exposure process is conducted, and then a development process, an etching process and a photoresist-removing process are conducted, thereby forming the pixel edge protective layer pattern. This mask is applicable for the preparation of an LTPS AMOLED; but if it is an LTPS LCD, then it is not necessary to use this mask in the preparation process for the corresponding patterning process.
In the above-described conventional manufacturing process of an LTPS TFT array substrate, by using the gate electrode as a barrier layer for ion-doping with respect to the source-drain region, the doped ions are adjacent to the channel region. In the Poly-Silicon annealing process, the doped ions partially diffuse toward the channel region, thereby decreasing the effective length of the channel region (the shortest distance between the source-drain regions). This not only makes the short channel effect of the channel region obvious, but also increases the coupling capacitance between the gate and source-drain, thereby degrading the TFT performance. In addition, such structure that the gate electrode and the gate line, also the source-drain electrode and the data line, exist respectively in two different layers, makes the preparation process complex.